Stanford researchers are building layers of logic and memory into skyscraper chips that are smaller, faster, cheaper – and taller.
At the IEEE International Electron Devices Meeting in San Francisco, December 15-17, a Stanford team revealed how to build high-rise chips that could leapfrog the performance of the single-story logic and memory chips on today’s circuit cards.
Research leader Subhasish Mitra, a Stanford Professor of electrical engineering and computer science, said:
This research is at an early stage, but our design and fabrication techniques are scalable. With further development this architecture could lead to computing performance that [...]