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High-Rise 3D Supercomputing Chips from Stanford

High-Rise 3D Supercomputing Chips from Stanford

by Giulio PriscoDecember 17, 2014

Stanford researchers are building layers of logic and memory into skyscraper chips that are smaller, faster, cheaper – and taller.

At the IEEE International Electron Devices Meeting in San Francisco, December 15-17, a Stanford team revealed how to build high-rise chips that could leapfrog the performance of the single-story logic and memory chips on today’s circuit cards.

Research leader Subhasish Mitra, a Stanford Professor of electrical engineering and computer science, said:

This research is at an early stage, but our design and fabrication techniques are scalable. With further development this architecture could lead to computing performance that is much, much greater than anything available today.

Stanford’s School of Engineering Professor H.-S. Philip Wong said:

With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand.

Nanoscale Elevators for Much Faster Computing

Stanford 3D Chip

Stanford engineers have created a four-layer prototype high-rise chip. In this representation, the bottom and top layers are logic transistors. Sandwiched between them are two layers of memory. The vertical tubes are nanoscale electronic “elevators” that connect logic and memory, allowing them to work together to solve problems.

The prototype chip unveiled at IEDM shows how to put logic and memory together into three-dimensional structures that can be mass-produced. In future operational chips, thousands of nanoscale electronic “elevators” will move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.

Three breakthroughs enabled these research results:

  • A new technology for creating transistors, those tiny gates that switch electricity on and off to create digital zeroes and ones.
  • A new type of computer memory that lends itself to multi-story fabrication.
  • A technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.

“Moore’s law” is the observation that computing performance increases exponentially. In the last few decades, the density of transistors in integrated circuits and many related performance indicators such as speed and memory have been doubling approximately every two years. Despite many gloomy predictions that computing performance would soon hit fundamental physical barriers, Moore’s law has proven remarkably accurate so far, and 3D chips may permit further exponential growth in the next decades.

Images from Stanford University and Shutterstock.

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